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HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS
HMS81004E HMS81008E HMS81016E HMS81024E HMS81032E
User's Manual (Ver. 1.00)
Version 1.00 Published by SP MCU Application Team (c)2001 Hynix Semiconductor, Inc. All right reserved.
Additional information of this manual may be served by Hynix Semiconductor offices in Korea or Distributors and Representatives listed at address directory. Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
HMS81004E/08E/16E/24E/32E
Table of Contents
1. OVERVIEW ...........................................1
Description .........................................................1 Features .............................................................1 Development Tools ............................................ 2
Oscillation Circuit .......................................... 34
11. BASIC INTERVAL TIMER ................36 12. WATCH DOG TIMER .......................38 13. Timer0, Timer1, Timer2 ....................39 14. INTERRUPTS ...................................47
Interrupt priority and sources ........................ 48 Interrupt control register ................................ 48 Interrupt accept mode ................................... 49 Interrupt Sequence ........................................ 50 BRK Interrupt ................................................ 52 Multi Interrupt ................................................ 52 External Interrupt ........................................... 52 Key Scan Input Processing ........................... 53
2. BLOCK DIAGRAM ..............................3 3. PIN ASSIGNMENT (Top View) ........... 4 4. PACKAGE DIMENSION .......................5 5. PIN FUNCTION .....................................8 6. PORT STRUCTURES .........................10 7. ELECTRICAL CHARACTERISTICS ...12
Absolute Maximum Ratings .............................12 Recommended Operating Conditions ..............12 DC Electrical Characteristics ............................12 REMOUT Port Ioh Characteristics Graph ........13 REMOUT Port Iol Characteristics Graph .........14 AC Characteristics ...........................................14
15.STANDBY FUNCTION ......................55
Sleep Mode .................................................... 55 STOP MODE .................................................. 55 STANDBY MODE RELEASE ......................... 56 RELEASE OPERATION OF STANDBYMODE58
8. MEMORY ORGANIZATION ................16
Registers ..........................................................16 Program Memory .............................................19 Data Memory ....................................................22 List for Control Registers.................................. 23 Addressing Mode .............................................25
16. RESET FUNCTION ..........................60
EXTERNAL RESET ...................................... 60 POWER ON RESET ..................................... 60 Low Voltage Detection Mode ........................ 62
9. I/O PORTS ..........................................30
R0 Ports ........................................................... 30 R1 Ports ...........................................................30 R2 Port .............................................................32
A. MASK ORDER SHEET ........................ i B. INSTRUCTION .................................... ii
Terminology List ...............................................ii Instruction Map ................................................. iii Instruction Set ..................................................iv
10. CLOCK GENERATOR ......................33
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HMS81004E/08E/16E/24E/32E
CMOS SINGLE- CHIP 8-BIT MICROCONTROLLER FOR UNIVERSAL REMOTE CONTROLLER
1. OVERVIEW
1.1 Description
The HMS81004E/08E/16E/24E/32E is an advanced CMOS 8-bit microcontroller with 4/8/16/24/32K bytes of ROM. The device is one of GMS800 family. The HYNIX HMS81004E/08E/16E/24E/32E is a powerful microcontroller which provides a highly flexible and cost effective solution to many UR applications.The HMS81004E/08E/16E/24E/32E provides the following standard features: 4/8/16/24/32K bytes of ROM, 448 bytes of RAM, 8-bit timer/counter, on-chip oscillator and clock circuitry. In addition, the HMS81004E/08E/16E/24E/32E supports power saving modes to reduce power consumption.
Device Name HMS81004E HMS81008E HMS81016E HMS81024E HMS81032E HMS81020TL HMS81032TL ROM Size 4K Bytes 8K Bytes 16K Bytes 24K Bytes 32K Bytes EPROM Size 20K Bytes 32K Bytes 448 Bytes ( included 256 bytes stack memory ) 20 SOP/PDIP 24 SOP/Skinny DIP 28 SOP/Skinny DIP RAM Size Package
1.2 Features
* Instruction Cycle Time: - 1us at 4MHz * Programmable I/O pins
20 PIN INPUT OUTPUT I/O 3 2 13 24 PIN 3 2 17 28 PIN 3 2 21
- Watch Dog Timer ............ 6Bit * 1ch * 8 Interrupt sources - Nested Interrupt control is available. - External input: 2 - Keyscan input - Basic Interval Timer - Watchdog timer - Timer : 3 * Power On Reset * Power saving Operation Modes - STOP Operation - SLEEP Operation * Low Voltage Detection Circuit * Watch Dog Timer Auto Start (During 1second after Power on Reset)
* Operating Voltage - 2.0 ~ 3.6 V @ 4MHz (MASK) - 2.0 ~ 4.0 V @ 4MHZ (OTP) * Timer - Timer / Counter ......... 16Bit * 1ch ......... 8Bit * 2ch - Basic Interval Timer ...... 8Bit * 1ch
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1.3 Development Tools
The HMS81004E/08E/16E/24E/32E are supported by a full-featured macro assembler, an in-circuit emulator CHOICE-Dr.TM and OTP programmers. Macro assembler operates under the MSWindows 95/98TM /NT4/W2000. Please contact sales part of HYNIX Software Hardware (Emulator) OTP programmer - MS- Window base assembler - Linker / Editor / Debugger - CHOICE-Dr. - CHOICE-Dr. EVA 81C5EVA - Universal single programmer. - 4 gang programmer - stand alone
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2. BLOCK DIAGRAM
G8MC Core
Watchdog Timer RAM
REMOUT R17/T0 R16/T1 R15/T2 R14/EC
R0 PORT
R00~R07
(448byte) Timer
R1 PORT
R12/INT2 R11/INT1
R10~R17
ROM Interrupt (32kbyte)
R00~R07 R10~R17
Key Scan INT. Generation Block R2 PORT
R20~R24
TEST RESET XIN XOUT
Clock Gen. & System Control
Prescaler & B.I.T
VDD
VSS
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3. PIN ASSIGNMENT (Top View)
R13 R12 R11 R10 VDD XOUT XIN R00 R01 R02 R03 R20 R21 R22
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28PIN
28 27 26 25 24 23 22 21 20 19 18 17 16 15
R14 R15 R16 R17 REMOUT RESET TEST R07 R06 R05 R04 VSS R24 R23
R13 R12 R11 R10 VDD XOUT XIN R00 R01 R02 R03 R20
1 2 3 4 5 6 7 8 9 10 11 12
24PIN
24 23 22 21 20 19 18 17 16 15 14 13
R14 R15 R16 R17 REMOUT RESET TEST R07 R06 R05 R04 VSS
R11 R10 VDD XOUT XIN R00 R01 R02 R03 R20
1 2 3 4 5 6 7 8 9 10
20PIN
20 19 18 17 16 15 14 13 12 11
R16 R17 REMOUT RESET TEST R07 R06 R05 R04 VSS
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4. PACKAGE DIMENSION
20 SOP
UNIT: INCH MAX MIN
0.229 0.291 0.419 0.398
0.105 0.093
0.012 0.004
0.512 0.495
0.013 0.008
0.020 0.013
0 ~ 8 0.042 0.016
0.050 BSC
20 PDIP
0.300 BSC 1.043 1.015 0.270 0.245
MAX 0.180
MIN 0.015 0.140 0.120
0.021 0.015
0.012 0.008
0 ~ 15
0.065 0.050
0.100 BSC
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24 SOP
UNIT: INCH MAX MIN
0.229 0.291 0.419 0.398
0.106 0.093
0.012 0.004
0.614 0.598
0.013 0.008
0.020 0.013
0 ~ 8 0.042 0.016
0.050 BSC
24 SKDIP
0.300 BSC 1.265 1.160 0.300 0.250
MAX 0.180
MIN 0.015 0.140 0.120
0.021 0.015
0 .0 1 4 0.008
0 ~ 15
0.065 0.045
0.100 BSC
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28 SOP UNIT: INCH MAX MIN
0.229 0.291 0.419 0.398
0.106 0.093
0.012 0.004
0.713 0.697
0.013 0.008
0.020 0.013
0 ~ 8 0.042 0.016
0.050 BSC
28 SKDIP
0.300 BSC 1.375 1.355 0.300 0.275
MAX 0.180
MIN 0.015 0.140 0.120
0.021 0.015
0 .0 1 4 0.008
0 ~ 15
0.055 0.045
0.100 BSC
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5. PIN FUNCTION
VDD: Supply voltage. VSS: Circuit ground. TEST: Used for shipping inspection of the IC. For normal operation, it should be connected to VDD. RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R1 serves the functions of the various following special features .
Port pin R11 R12 R14 R15 R16 R17 Alternate function INT1 (External Interrupt input 1) INT2 (External Interrupt input 2) EC (Event Counter input ) T2 (Timer / Counter input 2) T1 (Timer / Counter input 1) T0 (Timer / Counter input 0)
R20~R24: R2 is an 8-bit CMOS bidirectional I/O port. R2 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs .
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PIN NAME R00 R01 R02 R03 R04 R05 R06 R07 R10 R11/INT1 R12/INT2 R13 R14/EC R15/T2 R16/T1 R17/T0 R20 R21 R22 R23 R24 XIN XOUT REMOUT RESET TEST VDD VSS
INPUT/ OUTPUT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O O I I P P
Function
@RESET
@STOP
- Each bit of the port can be individually configured as an input or an output by user software - Push-pull output - CMOS input with pull-up resister (option) - Can be programmable as key scan input - Pull-up resisters are automatically disabled at output mode
INPUT
State of before Stop
- Each bit of the port can be individually configured as an input or an output by user software - Push-pull output - CMOS input with pull-up resister (option) - Can be programmable as key scan input or open drain output - Pull-up resisters are automatically disabled at output mode - Direct driving of LED(N-Tr.) - Each bit of the port can be individually configured as an input or an output by user software - Push-pull output - CMOS input with pull-up resister (option) - Pull-up resisters are automatically disabled at output mode - Direct driving of LED(N-Tr.) Oscillator input Oscillator output High current output Includes pull-up resistor Includes pull-up resistor Positive power supply Groud
INPUT
State of before Stop
INPUT
State of before Stop
Low High `L' output `L' level `L' output state of before stop
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6. PORT STRUCTURES
R0[0:7] R11/INT1, R12/INT2, R14/EC
LVD Circuit Pull up Reg. Open Drain Reg. Data Bus Data Reg. Pin VSS Dir R eg. VSS MUX Rd Key Scan Input KS_EN Standby Release Level Control Register Key Scan Input KS_EN MUX Tr.: Transistor Reg.: Register MUX Tr.: Transistor Reg.: Register
to R11...INT1 to R12...INT2 to R14...EC
LVD Circuit Pull up Reg. Open Drain Reg. Data Bus Data Reg.
OTP : connected MASK : option (default connected) VDD
OTP : connected MASK : option (default connected) VDD
Pull-up Tr.
Pull-up Tr.
VDD
VDD
Function Selection Reg.
Dir. Reg.
Pin
MUX Rd Noise Filter
R10, R13
Standby Release Level Control Register
LVD Circuit Pull up Reg. Open Drain Reg. Data Bus Data Reg.
OTP : connected MASK : option (default connected) VDD
Pull-up Tr.
VDD
Function Selection Reg.
Pin VSS
Dir R eg.
MUX Rd Key Scan Input KS_EN Standby Release Level Control Register MUX Tr.: Transistor Reg.: Register
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R15/T2, R16/T1, R17/T0
OTP : connected MASK : option (default connected) VDD
TEST
VDD VSS Noise Filter Pin
LVD Circuit Pull up Reg. Open Drain Reg. Data Bus Data Reg.
Pull-up Tr.
VDD
REMOUT
Pin VSS VDD
Function Selection Reg.
Dir R eg.
Internal Signal Pin
MUX Rd
to R15...T2 to R16...T1 to R17...T0
VSS
MUX
XIN, XOUT
Key Scan Input KS_EN
MUX Tr.: Transistor Reg.: Register
XOUT Noise Filter
XIN
Standby Release Level Control Register
R2[0:4]
from STOP circuit VSS OTP : connected MASK : option (default connected) VDD
LVD Circuit Pull up Reg. Open Drain Reg. Data Bus Data Reg.
RESET
VDD VSS
Pull-up Tr.
VDD
Noise Filter Pin from Power On Reset
Dir. Reg. VSS MUX Rd
Pin
Tr.: Transistor Reg.: Register
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7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage ........................................... -0.3 to +5.0 V Input Voltage .....................................-0.3 to VDD+0.3 V Output Voltage ...................................-0.3 to VDD+0.3 V Operating Temperature........................................ 0~70C Storage Temperature ...................................... -65~150C Power Dissipation................................................700 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
7.2 Recommended Operating Conditions
Specifications Parameter Supply Voltage Operating Frequency Operating Temperature Symbol VDD fXIN TOPR Condition Min. fXIN=4MHz VDD=2.0~3.6V 2.0 1.0 0 Max. 3.6 4.0 +70 V MHz C Unit
7.3 DC Electrical Characteristics
(TA=-0~70C, VDD=2.0~3.6V, GND=0V)
Specifications Parameter High level input Voltage Low level input Voltage Hign level input Leakage Current Low level input Leakage Current High level output Voltage Symbol VIH1 VIH2 VIL1 VIL2 IIH IIL VOH1 VOH2 VOH3 VOL1 Low level output Voltage Hign level output Leakage Current Low level output Leakage Current VOL2 VOL3 IOHL IOLL Condition Min. R11,R12,R14,RESET R0,R1(except R11,R12,R14), R2 R11,R12,R14,RESET R0,R1(except R11,R12,R14), R2 R0,R1,R2,RESET ,VIH= VDD R0,R1,R2,RESET (without pull-up),VIL= 0 R0, IOH=-0.5mA R1[6:0], R2, IOH=-1.0mA XIN, XOUT,IOH=-200A R0, IOL=1mA R1, R2, IOL=5mA XIN, XOUT,IOL=200A R0,R1,R2, VOH= VDD R0,R1,R2, VOL= 0 0.8 VDD 0.7 VDD 0 0 VDD-0.4 VDD-0.4 VDD-0.9 Typ. Max. VDD VDD 0.2 VDD 0.3 VDD 1 -1 0.4 0.8 0.8 1 -1 V V V V A A V V V V V V A A Unit
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Specifications Parameter High Level output current Low Level output cruuent Input pull-up current Symbol IOH IOL Ip IDD1 IDD2 ISLP1 Power Supply Current ISLP2 ISTP1 ISTP2 RAM retention supply voltage VRET Condition Min. REMOUT, R17, VOH =2V REMOUT, VOL =1V R0,R1,R2, RESET, VDD=3V Operating current ,fxin=4Mhz, VDD=2.0V Operating current ,fxin=4Mhz, VDD=3.6V Sleep mode current ,fxin=4Mhz, VDD=2.0V Sleep mode current ,fxin=4Mhz, VDD=3.6V Stop mode current ,Oscillator Stop VDD=2.0V Stop mode current ,Oscillator Stop VDD=3.6V -30 0.5 15 0.7 Typ. -12 30 2.4 4 1 2 2 3 Max. -5 3 60 6 10 2 3 8 10 mA mA A mA mA mA mA A A V Unit
7.4 REMOUT Port Ioh Characteristics Graph
(typical process & room temperature)
.
Ioh(mA) 0
Vdd 2V Vdd 3V
-5
-10
-15
Vdd 4V
-20
-25
-30 0 0.5 1.0 1.5 Voh (V) 2.0 2.5 3.0 3.5 4.0
Figure 7-1 Ioh vs Voh
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7.5 REMOUT Port Iol Characteristics Graph
(typical process & room temperature)
.
Iol(mA) 5
4
Vdd 4V
3
2
Vdd 3V
1
0
Vdd 2V
-1 0 0.5 1.0 1.5 Vol (V) 2.0 2.5 3.0 3.5 4.0
Figure 7-2 Iol vs Vol
7.6 AC Characteristics
(TA=0~+70C, VDD=2.0~3.6V, VSS=0V)
Specifications Parameter External clock input cycle time System clock cycle time External clock pulse width High External clock pulse width Low External clock rising time External clock falling time Interrupt pulse width High Interrupt pulse width Low RESET Input pulse width low Event counter input pulse width high Event counter input pulse width low Event counter input pulse rising time Event counter input pulse falling time Symbol tCP tSYS tCPH tCPL tRCP tFCP tIH tIL tRSTL tECH tECL tREC tFEC XIN XIN XIN XIN INT1, INT2 INT1, INT2 RESET EC EC EC EC Pins Min. XIN 250 500 40 40 2 2 8 2 2 Typ. 500 1000 Max. 1000 2000 40 40 40 40 ns ns ns ns ns nS tSYS tSYS tSYS tSYS tSYS ns ns Unit
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tCP
tCPH
tCPL VDD-0.5V
XIN
tRCP tIH tIL tFCP
0.5V
INT1 INT2
0.8VDD 0.2VDD
tRSTL
RESET
0.2VDD
tECH
tECL 0.8VDD 0.2VDD
EC
Figure 7-3 Timing Diagram
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8. MEMORY ORGANIZATION
The HMS81004E/08E/16E/24E/32E has separate address spaces for Program memory and Data Memory. Program memory can only be read, not written to. It can be up to 32K bytes of Program memory. Data memory can be read and written to up to 448 bytes including the stack area.
8.1 Registers
This device has six registers that are the Program Counter (PC), an Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register.
A X Y SP PCH PCL PSW ACCUMULATOR X REGISTER Y REGISTER STACK POINTER
X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. * X Register In the case of division instruction, execute as register.
PROGRAM COUNTER PROGRAM STATUS WORD
* Y Register In the case of 16-bit operation instruction, execute as the upper 8-bit of YA. (16-bit accumulator). In the case of multiplication instruction, execute as a multiplicand register. After multiplication operation, the upper 8-bit of the result enters. In the case of division instruction, execute as the upper 8-bit of dividend. After division operation, remains enters. Y register can be used as loop counter of conditional branch command. (e.g.DBNE Y, rel) Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts, calling out subroutines and PUSH, POP, RETI, RET instruction. Stack Pointer identifies the location in the stack to be accessed (save or restore). Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The SP is post-decremented when a subroutine call or a push instruction is executed, or when an interrupt is accepted. The SP is pre-incremented when a return or a pop instruction is executed. The stack can be located at any position within 100H to 1FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "FFH" is
Figure 8-1 Configuration of Registers
Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below. In the case of multiplication instruction, execute as a multiplier register. After multiplication operation, the lower 8bit of the result enters. (Y*A => YA). In the case of division instruction, execute as the lower 8-bit of dividend. After division operation, quotient enters.
Y
Y A
A
Two 8-bit Registers can be used as a "YA" 16-bit Register
Figure 8-2 Configuration of YA 16-bit Register
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used.
Stack Address ( 100H ~ 1FFH ) 15 01H 8 7 SP 0
Caution: The Stack Pointer must be initialized by software because its value is undefined after RESET. Example: To initialize the SP
Hardware fixed
LDX TXSP
#0FFH
; SP FFH
At execution of a CALL/TCALL/PCALL
At acceptance of interrupt
At execution of RET instruction
At execution of RETI instruction
01FC 01FD 01FE 01FF PCL PCH Push down
01FC 01FD 01FE 01FF PSW PCL PCH Push down
01FC 01FD 01FE 01FF PCL PCH Pop up
01FC 01FD 01FE 01FF PSW PCL PCH Pop up
SP before execution SP after execution
01FF 01FD
01FF 01FC
01FD 01FF
01FC 01FF
At execution of PUSH instruction PUSH A (X,Y,PSW) 01FC 01FD 01FE 01FF A Push down
At execution of POP instruction POP A (X,Y,PSW) 01FC 01FD 01FE 01FF A Pop up 01FFH 0100H
Stack depth
SP before execution SP after execution
01FF 01FE
01FE 01FF
Figure 8-3 Stack Operation
Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that
reflect the current state of the CPU. The PSW is described in Figure 8-4 . It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction.
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[Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result.
MSB PSW NEGATIVE FLAG OVERFLOW FLAG SELECT DIRECT PAGE when g=1, page is addressed by RPR BRK FLAG
LSB
N
V
G
B
H
I
Z
C
RESET VALUE : 00H CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS
Figure 8-4 PSW (Program Status Word) Register
[Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address. [Direct page flag G] This flag assigns RAM page for direct addressing mode. In
the direct addressing mode, addressing area is from zero page 00H to 0FFH when this flag is "0". If it is set to "1", addressing area is 1 Page. It is set by SETG instruction and cleared by CLRG. [Overflow flag V] This flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH) or -128(80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
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8.2 Program Memory
A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 4/8/16/24/32K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 8-5 , shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 8-6 . As shown in Figure 8-5 , each area is assigned a fixed location in Program Memory. Program Memory area contains the user program.
8000H
Example: Usage of TCALL
LDA #5 TCALL 0FH : : ;1BYTE INSTR UCTIO N ;INSTEAD OF 2 BYTES ;NOR M AL C ALL
; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0 RET ; FUNC_B: LDA LRG1 2 RET ; ;TABLE CALL ADD. AREA ; ORG 0FFC0H DW FUNC_A DW FUNC_B
1
;TCALL ADDRESS AREA
A000H
HMS81032E 32KROM
C000H HMS81024E 24KROM
E000H HMS81016E 16KROM
HMS81008E 8KROM
F000H HMS81004E 4KROM
The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte interval: 0FFF8H and 0FFF9H for External Interrupt 1, 0FFFAH and 0FFFBH for External Interrupt 0, etc. Any area from 0FF00H to 0FFFFH, if it is not going to be used, its service location is available as general purpose Program Memory.
Address 0FFDEH E0 E2 E4 E6 E8 EA EC EE F0 F2 F4 F6 F8 FA FC FE Vector Area Memory S/W Interrupt Vector Area Basic Interval Timer Interrupt Vector Area Watch Dog Timer Interrupt Vector Area Timer2 Interrupt Vector Area Timer1 Interrupt Vector Area Timer0 Interrupt Vector Area External Interrupt 2 Vector Area External Interrupt 1 Vector Area Key Scan Interrupt Vector Area RESET Vector Area
FF00H FFC0H FFE0H FFFFH
PCALL AREA TCALL AREA INTERRUPT VECTOR AREA
Figure 8-5 Program Memory Map
Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in Figure 8-7 .
NOTE: "-" means reserved area.
Figure 8-6 Interrupt Vector Area
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Address 0FFC0H C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
Program Memory TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK *
Address 0FF00H
PCALL Area Memory
PCALL Area (192 Bytes)
0FFBFH
NOTE: * means that the BRK software interrupt is using same address with TCALL0.
Figure 8-7 PCALL and TCALL Memory Area
PCALL rel
4F35 PCALL 35H
TCALL n
4A TCALL 4
4F 35
4A
01001010
~ ~ ~ ~
0D125H NEXT
~ ~
Reverse
~ ~
0FF00H 0FF35H NEXT
PC: 11111111 11010110 FH FH DH 6H
0FF00H 0FFD6H 25 D1
0FFFFH
0FFD7H 0FFFFH
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Example: The usage software example of Vector address and the initialize part.
ORG DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW ORG 0FFE0H NOT_USED NOT_USED NOT_USED BIT_INT WDT_INT NOT_USED NOT_USED TMR2_INT TMR1_INT TMR0_INT NOT_USED INT2 INT1 KEY_INT NOT_USED RESET 08000H
; BIT ; Watch Dog Timer ; ; ; ; ; ; ; ; ; Timer-2 Timer-1 Timer-0 Int.2 Int.1 Key Scan Reset
;HMS81032E Program start address
;******************************************** ; MAIN PROGRAM * ;******************************************** ; RESET: NOP CLRG DI ;Disable All Interrupts LDX #0 RAM_CLR: LDA #0 ;RAM Clear(!0000H->!00BFH) STA {X}+ CMPX #0C0H BNE RAM_CLR ; LDX TXSP LDM LDM LDM LDM : : LDM : : #0FFH R0, #0 R0DD,#1000_0010B P0PC,#1000_0010B PMR1,#0000_0010B CKCTLR,#0011_1101B ;Stack Pointer Initialize ;Normal Port 0 ;Normal Port Direction ;Pull Up Selection Set ;R1 port / int ;WDT ON , 16mS Time delay after stop mode release
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8.3 Data Memory
Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into 3 groups, a user RAM, control registers, Stack.
0000H
Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section.
RAM (192 Bytes) PAGE0 00BFH 00C0H 00FFH 0100H RAM (STACK) (256 Bytes) PAGE1 CONTROL REGISTERS
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction.
Example; To write at CKCTLR
LDM CLCTLR,#09H ;Divide ratio /16
01FFH
Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-3 on page 17.
Figure 8-8 Data Memory Map
User Memory The HMS81004E/08E/16E/24E/32E has 448 x 8 bits for the user memory (RAM). Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0H to 0FFH.
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8.4 List for Control Registers
Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h Function Register PORT R0 DATA REG. PORT R0 DATA DIRECTION REG. PORT R1 DATA REG. PORT R1 DATA DIRECTION REG. PORT R2 DATA REG. PORT R2 DATA DIRECTION REG. reserved CLOCK CONTROL REG. BASIC INTERVAL REG. WATCH DOG TIMER REG. PORT R1 MODE REG. INT. MODE REG. EXT. INT. EDGE SELECTION INT. ENABLE REG. LOW INT. REQUEST FLAG REG. LOW INT. ENABLE REG. HIGH INT. REQUEST FLAG REG. HIGH TIMER0 (16bit) MODE REG. TIMER1 (8bit) MODE REG. TIMER2 (8bit) MODE REG. TIMER0 HIGH-MSB DATA REG. TIMER0 HIGH-LSB DATA REG. TIMER0 LOW-MSB DATA REG. TIMER0 HIGH-MSB COUNT REG. TIMER0 LOW-LSB DATA REG. TIMER0 LOW-LSB COUNT REG. TIMER1 HIGH DATA REG. TIMER1 LOW DATA REG. TIMER1 LOW COUNT REG. TIMER2 DATA REG. TIMER2 COUNT REG. TIMER0 / TIMER1 MODE REG. Reserved STANDBY MODE RELEASE REG0 STANDBY MODE RELEASE REG0 PORT R1 OPEN DRAIN ASSIGN REG. SMPR0 SMPR1 R1ODC R/W R/W R/W 00000000b 00000000b 00000000b TM01 T2DR T1HD T1LD T0LLD CKCTLR BTR WDTR PMR1 IMOD IEDS IENL IRQL IENH IRQH TM0 TM1 TM2 T0HMD T0HLD T0LMD W R W W R/W W R/W R/W R/W R/W R/W R/W R/W W W W R W W W W R W R R/W --110111b undefined -0001111b 00000000b -0000000b 00000000b -00-----b -00-----b 000-000-b 000-000-b 00000000b 00000000b 00000000b undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 00000000b R0 R0DD R1 R1DD R2 R2DD Symbol Read Write R/W W R/W W R/W W RESET Value undefined 00000000b undefined 00000000b undefined 00000000b
00D6h 00D7h 00D8h
00D9h 00DAh 00DBh 00DCh 00DDh 00DEh
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00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh
PORT R2 OPEN DRAIN ASSIGN REG. Reserved Reserved Reserved Reserved PORT R0 OPEN DRAIN ASSIGN REG. Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SLEEP MODE REG. Reserved Reserved Reserved Reserved Reserved STANDBY RELEASE LEVEL CONT. REG. 0 STANDBY RELEASE LEVEL CONT. REG. 1 PORT R0 PULL-UP REG. CONT. REG. PORT R1 PULL-UP REG. CONT. REG. PORT R2 PULL-UP REG. CONT. REG. Reserved Reserved Reserved Reserved Reserved
R2ODC
R/W
00000000b
R0ODC
R/W
00000000b
SLPM
W
- - - - - - - 0b
SRLC0 SRLC1 R0PC R1PC R2PC
W W W W W
00000000b 00000000b 00000000b 00000000b 00000000b
W
Registers are controlled by byte manipulation instruction such as LDM etc., do not use bit manipulation instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers, content of other seven bits are may varied to unwanted value. Registers are controlled by both bit and byte manipulation instruction.
R/W
- : this bit location is reserved.
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8.5 Addressing Mode
The HMS81004E/08E/16E/24E/32E uses six addressing modes; * Register addressing * Immediate addressing * Direct page addressing * Absolute addressing * Indexed addressing * Register-indirect addressing
0C35H data data 55H
E45535
LDM
35H,#55H
0F100H 0F101H 0F102H
~ ~
E4 55 35
~ ~
(1) Register Addressing Register addressing accesses the A, X, Y, C and PSW. (2) Immediate Addressing #imm In this mode, second byte (operand) is accessed as a data immediately. Example:
0435 ADC #35H
35H MEMORY data
(3) Direct Page Addressing dp In this mode, a address is specified within direct page. Example; G=0
C535 LDA 35H ;A RAM[35H]
~ ~
~ ~
04 35 A+35H+C A 0E550H 0E551H C5 35
data A
When G-flag is 1, then RAM address is difined by 16-bit address which is composed of 8-bit RAM paging register (RPR) and 8-bit immediate data. Example: G=1, RPR=0CH
(4) Absolute Addressing !abs Absolute addressing sets corresponding memory data to Data , i.e. second byte(Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example;
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0735F0
ADC
!0F035H
;A ROM[0F035H]
0F035H
data
~ ~
A+data+C A
~ ~
0F100H 0F101H 0F102H 07 35 F0
address: 0F035
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The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H regardless of G-flag and RPR.
983501 INC !0135H ;A ROM[135H]
X indexed direct page, auto increment {X}+ In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; G=0, X=35H
DB LDA {X}+
135H
data
~ ~
~ ~
0F100H 0F101H 0F102H 98 35 01

data+1 data
35H
data
~ ~
data A
~ ~
DB
address: 0135
36H X
(5) Indexed Addressing X indexed direct page (no offset) {X} In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H, G=1, RPR=01H
D4 LDA {X} ;ACCRAM[X].
X indexed direct page (8 bit offset) dp+X This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; G=0, X=0F5H
C645 LDA 45H+X
115H
data
~ ~
data A
~ ~
0E550H D4
3AH
data
~ ~
0E550H 0E551H C6 45
~ ~

data A
45H+0F5H=13AH
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Y indexed direct page (8 bit offset) dp+Y This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. Y indexed absolute !abs+Y Sets the value of 16-bit absolute address plus Y-register data as Memory. This addressing mode can specify memory in whole area. Example; Y=55H
D500FA LDA !0FA00H+Y
3F35
JMP
[35H]
35H 36H
0A E3
~ ~
0E30AH NEXT
~ ~
jump to address 0E30AH
~ ~
0FA00H 3F 35
~ ~
0F100H 0F101H 0F102H
D5 00 FA
0FA00H+55H=0FA55H
X indexed indirect [dp+X] Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plusX-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, X=10H
1625 ADC [25H+X]
~ ~
0FA55H data
~ ~

data A
(6) Indirect Addressing Direct page indirect [dp] Assigns data address to use for accomplishing command which sets memory data(or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL Example; G=0
0FA00H 35H 36H 05 E0
~ ~
0E005H data
~ 0E005H ~
25 + X(10) = 35H
~ ~
~ ~
16 25
A + data + C A
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Y indexed indirect [dp]+Y Processes momory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct pageplus Y-register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, Y=10H
1725 ADC [25H]+Y
Absolute indirect [!abs] The program jumps to address specified by 16-bit absolute address. JMP Example; G=0
1F25E0 JMP [!0C025H]
PROGRAM MEMORY
25H 26H
05 E0
0E025H 0E026H
25 E7
~ ~
0E015H data
~ ~
0E005H + Y(10) = 0E015H
~ ~
~ ~
NEXT
jump to address 0E30AH
~ ~
0E725H
~ ~
0FA00H 17 25
~ ~
0FA00H 1F 25 E0
~ ~
A + data + C A
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9. I/O PORTS
The HMS81004E/08E/16E/24E/32E has 24 I/O ports which are PORT0(8 I/O), PORT1 (8 I/O), PORT2 (8 I/O). Pull-up resistor of each port can be selectable by program. Each port contains data direction register which controls I/ O and data register which stores port data. (1) R0 I/O Data Direction Register (R0DD) R0 I/O Data Direction Register (R0DD) is 8-bit register, and can assign input state or output state to each bit. If R0DD is "1", port R0 is in the output state, and if "0", it is in the input state. R0DD is write-only register. Since R0DD is initialized as "00h" in reset state, the whole port R0 becomes input state. (2) R0 Data Register (R0) R0 data register (R0) is 8-bit register to store data of port R0. When set as the output state by R0DD, and data is written in R0, data is outputted into R0 pin. When set as the input state, input state of pin is read. The initial value of R0 is unknown in reset state. (3) R0 Open drain Assign Register (R0ODC)
R0 Data Register (R/W) R0 ADDRESS : 0C0H RESET VALUE : Undefined
9.1 R0 Ports
R0 is an 8-bit CMOS bidirectional I/O port (address 0C0H). Each I/O pin can independently used as an input or an output through the R0DD register (address 0C1H). R0 has internal pull-ups that is independently connected or disconnected by R0PC. The control registers for R0 are shown below.
R07 R06 R05 R04 R03 R02 R01 R00
R0 Direction Register (W) R0DD
ADDRESS : 0C1H RESET VALUE : 00H
R0 Open Drain Assign Register (R0ODC) is 8bit register, and can assign R0 port as open drain output port each bit, if corresponding port is selected as output. If R0ODC is selected as "1", port R0 is open drain output, and if selected as, "0" it is push-pull output. R0ODC is write-only register and initialized as "00h" in reset state. (4) R0 Pull-up Control Register (R0PC)
Port Direction 0: Input 1: Output ADDRESS :0F8H RESET VALUE : 00H
R0 Pull-up Control Register (W) R0PC
Pull-up select 1: Without pull-up 0: With pull-up
R0 Pull-up Control Register (R0PC) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. If R0PC is selected as "1", pull-up ia disabled and if selected as "0", it is enabled. R0PC is writeonly register and initialized as "00h" in reset state. The pull-up is automatically disabled, if corresponding port is selected as output.
R0 Open drain Assign Register (W) ADDRESS :0E4H RESET VALUE : 00H R0ODC Open drain select 0: Push-pull 1: Open drain
9.2 R1 Ports
R1 is an 8-bit CMOS bidirectional I/O port (address 0C2H). Each I/O pin can independently used as an input or an output through the R1DD register (address 0C3H). R1 has internal pull-ups that is independently connected or disconnected by register R1PC. The control registers for R1 are shown below.
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R1 Data Register (R/W) R1
ADDRESS : 0C2H RESET VALUE : Undefined
R17 R16 R15 R14 R13 R12 R11 R10
and can assign R1 port as open drain output port each bit, if corresponding port is selected as output. If R1ODC is selected as "1", port R1 is open drain output, and if selected as "0", it is push-pull output. R1ODC is write-only register and initialized as "00h" in reset state. (4) R1 Port Mode Register (PMR1) R1 Port Mode Register (PMR1) is 8-bit register, and can assign the selection mode for each bit. When set as "0", corresponding bit of PMR1 acts as port R1 selection mode, and when set as "1", it becomes function selection mode. PMR1 is write-only register and initialized as "00h" in reset state. Therefore, becomes Port selection mode. Port R1 can be I/O port by manipulating each R1DD bit, if corresponding PMR1 bit is selected as "0".
R1 Direction Register (W) R1DD
ADDRESS : 0C3H RESET VALUE : 00H
Port Direction 0: Input 1: Output ADDRESS : 0F9H RESET VALUE : 00H
R1 Pull-up Control Register (W) R1PC
Pull-up select 1: Without pull-up 0: With pull-up
R1 Open drain Assign Register (W) ADDRESS : 0DEH RESET VALUE : 00H P1ODC Open drain select 0: Push-pull 1: Open drain
Pin Name T0S
PMR1 0 1 0 1 0 1 0 1
Selection Mode R17 (I/O) T0 (O) R16 (I/O) T1 (O) R15 (I/O) T2 (O) R14 (I/O) EC (I)
Remarks Timer0 Timer1 Timer2 Timer0 Event
R1 Port Mode Register (W) PMR1
ADDRESS : 0C9H RESET VALUE : 00H
T1S
T2S
Mode select 0: Port R1 selection 1: Function selection
ECS
(1) R1 I/O Data Direction Register (R1DD) R1 I/O Data Direction Register (R1DD) is 8-bit register, and can assign input state or output state to each bit. If R1DD is "1", port R1 is in the output state, and if "0", it is in the input state. R1DD is write-only register. Since R1DD is initialized as "00h" in reset state, the whole port R1 becomes input state. (2) R1 Data Register (R1)
INT2S
0 1 0 1
R12 (I/O) INT2 (I) R11 (I/O) INT1 (I) Timer0 Input Capture
INT1S
Table 9-1 Selection mode of PMR1 R1 data register (R1) is 8-bit register to store data of port R1. When set as the output state by R1DD, and data is written in R1, data is outputted into R1 pin. When set as the input state, input state of pin is read. The initial value of R1 is unknown in reset state. (3) R1 Open drain Assign Register (R1ODC) R1 Open Drain Assign Register (R1ODC) is 8bit register,
(5) R1 Pull-up Control Register (R1PC) R1 Pull-up Control Register (R1PC) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. If R1PC is selected as "1", pull-up ia disabled and if selected as "0", it is enabled. R1PC is writeonly register and initialized as "00h" in reset state. The
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pull-up is automatically disabled, if corresponding port is selected as output.
9.3 R2 Port
R2 is an 8-bit CMOS bidirectional I/O port (address 0C4H). Each I/O pin can independently used as an input or an output through the R2DD register (address 0C5H). R2 has internal pujll-ups that is independently connected or disconnected by R2PC (address 0FAH). The control registers for R2 are shown as below.
(1) R2 I/O Data Direction Register (R2DD) R2 I/O Data Direction Register (R2DD) is 8-bit register, and can assign input state or output state to each bit. If R2DD is "1", port R2 is in the output state, and if "0", it is in the input state. R2DD is write-only register. Since R2DD is initialized as "00h" in reset state, the whole port R2 becomes input state. (2) R2 Data Register (R2) R2 data register (R2) is 8-bit register to store data of port R2. When set as the output state by R2DD, and data is written in R2, data is outputted into R2 pin. When set as the input state, input state of pin is read. The initial value of R2 is unknown in reset state. (3) R2 Open drain Assign Register (R2ODC) R2 Open Drain Assign Register (R2ODC) is 8bit register, and can assign R2 port as open drain output port each bit, if corresponding port is selected as output. If R2ODC is selected as "1", port R2 is open drain output, and if selected as "0", it is push-pull output. R2ODC is write-only register and initialized as "00h" in reset state. (4) R2 Pull-up Control Register (R2PC) R2 Pull-up Control Register (R2PC) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. If R2PC is selected as "1", pull-up ia disabled and if selected as "0", it is enabled. R2PC is writeonly register and initialized as "00h" in reset state. The pull-up is automatically disabled, if corresponding port is selected as output.
R2 Data Register (R/W) R2 -
ADDRESS : 0C4H RESET VALUE : Undefined R24 R23 R22 R21 R20
R2 Direction Register (W) R2DD
ADDRESS : 0C5H RESET VALUE : 00H
Port Direction 0: Input 1: Output ADDRESS :0FAH RESET VALUE : 00H
R2 Pull-up Control Register (W) R2PC
Pull-up select 1: Without pull-up 0: With pull-up
R2 Open drain Assign Register (W) ADDRESS :0DFH RESET VALUE : 00H R2ODC Open drain select 0: Push-pull 1: Open drain
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10. CLOCK GENERATOR
Clock generating circuit consists of Clock Pulse Generator (C.P.G), Prescaler, Basic Interval Timer (B.I.T) and Watch Dog Timer. The clock applied to the Xin pin divided by two is used as the internal system clock. Prescaler consist of 12-bit binary counter. The clock supplied from oscillation circuit is input to prescaler(fex) The divided output from each bit of prescaler is provided to periphera hardwarel Clock to peripheral hardware can be stopped by bit4 (ENPCK) of CKCTLR Register. ENPCK is set to "1" in reset
ENPCK 0: Stopped 1: Provided
state.
Clock Control Register (W) CKCTLR 7 6 5 4 3 ADDRESS : 0C7H INITIAL VALUE : --110111b 2 1 0
OSC CIRCUIT
fex
CLOCK PULSE GENERATOR
Internal system clock (CPU clock)
PRESCALER PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12
/1
/2
/4
/8
/16
/32
/64
/128
/256
/512 /1024 /2048 /4096
Peripheral clock
fEX(MHz)
4 Frequency period
PS0 4M 250n
PS1 2M 500n
PS2 1M 1u
PS3 500K 2u
PS4 250K 4u
PS5 125K 8u
PS6 62.5K 16u
PS7 31.25K 32u
PS8 15.63K 64u
PS9
PS10
PS11
PS12
7.183K 3.906K 128u 256u
1.953K 0.976K 512u 1024u
Figure 10-1 Block diagram of Clock Generator
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10.1 Oscillation Circuit
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Figure 10-2 shows circuit diagrams using a crystal (or ceramic) oscillator. As shown in the diagram, oscillation circuits can be constructed by connecting a oscillator between Xout and Xin. Colck from oscillation circuit makesCPU clock via clock pulse generator, and then enters prescaler to make peripheral hardware clock. Alternately, the oscillator may be driven from an esternal source as Figure 10-3 . In the STOP mode,oscillation stop, Xout state goes to "HIGH" , Xin state goes to "LOW" , and built-in feed back resistor is disabled. Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. In addition, see Figure 104 for the layout of the crystal.
Note: Minimize the wiring length. Do not allow the wiring to intersect with other signal conductors. Do not allow the wiring to come near changing high current. Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do not ground it to any ground pattern where high current is present. Do not fetch signals from the oscillator.
Cout Cin
Xout
Xin Vss XOUT XIN
Figure 10-2 External Crystal(Ceramic) oscillator circuit
OPEN
Xout
External Clock Source
Xin Vss
Figure 10-4 Recommend Layout of Oscillator PCB circuit
Figure 10-3 External clock input circuit
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Frequency
Resonator Maker CQ CQ
Part Name ZTT2.00 ZTA2.00 CSTLS2M00G56-B0 CSTCC2.00MG0H6 CSTCC2M00G56-R0 ZTT4.00 ZTA4.00 CSTS0400MG06 CSTLS4M00G56-B0 CSTCR4M00G55-R0 FCR4.0MC5 FCR4.0MSC5 CRT4.00MS CRM4.00MS
Load Capacitor Cin=Cout=open Cin=Cout=30pF Cin=Cout=open Cin=Cout=open Cin=Cout=open Cin=Cout=open Cin=Cout=30pF Cin=Cout=open Cin=Cout=open Cin=Cout=open Cin=Cout=open Cin=Cout=open Cin=Cout=open Cin=Cout=30pF
Operating Voltage 2.0~3.6 2.0~3.6 2.0~3.6 2.0~3.6 2.0~3.6 2.0~3.6 2.0~3.6 2.0~3.6 2.0~3.6 2.0~3.6 2.0~3.6 2.0~3.6 2.0~3.6 2.0~3.6
2.00MHz
MURATA MURATA MURATA CQ CQ MURATA MURATA
4.00MHz
MURATA TDK TDK CORETECK CORETECK
Table 10-1 Recommendalbe resonator
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11. BASIC INTERVAL TIMER
The HMS81004E/08E/16E/24E/32E has one 8-bit Basic Interval Timer that is free-run and can not stop. Block diagram is shown in Figure 11-1 . The Basic Interval Timer generates the time base for Standby release time, watchdog timer counting, and etc. It also provides a Basic interval timer interrupt (IFBIT). As the count overflow from FFH to 00H, this overflow causes the interrupt to be generated. -8bit binary up-counter -Use the bit output of prescaler as input to secure the oscillation stabilization time after power-on -Secures the oscillation stabilization time in standby mode (stop mode) release -Contents of B.I.T can be read -Provides the clock for watch dog timer The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 11-2 . If bit3(BTCL) of CKCTLR is set to "1", B.I.T is cleared, and then, after one machine cycle, BTCL becomes "0", and B.I.T starts counting. BTCL is set to 0 in reset state. The input clock of B.I.T can be selected from the prescaler within a range of 2us to 256us by clock input selection bits (BTS2~BTS0). (at fex = 4MHz). In reset state, or power on reset, BTS2="1", BTS1= "1", BTS0= "1" to secure the longest oscillation stabilization time. B.I.T can generate the wide range of basic interval time interrupt request (IFBIT) by selecting prescaler output. By reading of the Basic Interval Timer Register (BITR), we can read counter value of B.I.T. Because B.I.T can be cleared or read, the spending time up to maximum 65.5ms can be available. B.I.T is read-only register. If B.I.T register is written, then CKCTLR register with same address is written.
/8 /16 /32
Prescaler
/64 /128 /256 /512 /1024
MUX
source clock
Basic Interval Timer overflow 8-bit up-counter IFBIT Basic Interval Timer Interrupt To Watchdog timer (WDTR)
clear
Select Input clock 3 BTS[2:0] [0C7H] clock control register Internal bus line CKCTLR BTCL BITR Read
Figure 11-1 Block diagram of Basic Interval Timer
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CKCTLR
7 -
6 -
W W W W 3 2 1 0 BTCL WDTON ENPCK BTCL BTS2 BTS1 BTS0
W 5
W 4
ADDRESS: 0C7H INITAIL VALUE: --110111B
Caution:
Both register are in same address, when write, to be a CKCTLR, when read, to be a BITR.
Basic Interval Timer source clock select 000: fXIN / 8 001: fXIN / 16 010: fXIN / 32 011: fXIN / 64 100: fXIN / 128 101: fXIN / 256 110: fXIN / 512 111: fXIN / 1024 Clear bit 0: Normal operation, free-run 1: Clear 8-bit counter (BITR) to "0" and count up again. This bit becomes to "0" automatically after one machine cycle. Periphral clock 0:stopped 1:provided Watch Dog Timer function control 0:6bit timer 1:Watch Dog Timer
R 7
R 6
R 5
R 4
BITR
R 3 BTCL
R 2
R 1
R 0
ADDRESS: 0C7H INITIAL VALUE: Undefined
8-BIT FREE-RUN BINARY COUNTER
Figure 11-2 CKCTLR AND BITR B.I.T. Input clock@4Mhz(us) 2 4 8 16 32 64 128 256 Standby release time(ms) 0.512 1.024 2.048 4.096 8.192 16.384 32.768 65.536
BTS[2:0] 000 001 010 011 100 101 110 111
CPU Source clock /8 /16 /32 /64 /128 /256 /512 /1024
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12. WATCH DOG TIMER
Watch Dog Timer (WDT) consists of 6-bit binary counter, 6-bit comparator, and Watch Dog Timer Register (WDTR).Watch Dog Timer can be used 6-bit general Timer or specific Watch dog timer by setting bit5 (WDTON) of Clock Control Register (CKCTLR).By assigning bit6(WDTCL) of WDTR, 6-bit counter can be cleared. WDT Interrupt (IFWDT) interval is determined by the interrupt IFBIT interval of Basic Interval Timer and the value of WDT Register. -Interval of IFWDT = (IFBIT interval) * (WDTR value) As IFBIT (Basic Interval Timer Interrupt Request) is used for input clock of WDT, Input clock cycle is possible from 512 us to 65,536 us by BTS. (at fex = 4MHz) *At Hardware reset time,WDT starts automatically. Therefore the user must select the CKCTLR and WDTR before WDT overflow. -Reset WDTR value = 0Fh,=15 -Interval of WDT = 65,536 * 15 = 983040 us (about 1second )
7
6
5
4
3
2
1
0
WDTR
-
WDTCL WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0 BTCL
ADDRESS: 0C8H INITIAL VALUE: -0001111b
Watch Dog Timer Operation 0:Free-run 1:Automatically cleared, after one machine cycle
WDTON
IFBIT
WDT (6-bit)
To Reset circuit WDT INTERRUPT
IFWDT Clear 6 WDTR (6-bit) [0C8H] Comparator
WDT
Figure 12-1 Block diagram of Watch Dog Timer
Device come into the reset state by WDT Note: When WDTR Register value is 63 (3Fh) (Caution) : Do not use "0" for WDTR Register value.
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13. Timer0, Timer1, Timer2
(1) Timer Operation Mode Timer consists of 16bit binary counter Timer0 (T0), 8bit binary Timer1 (T1), Timer2 (T2), Timer Data Register, Timer Mode Register (TM01, TM0, TM1, TM2) and control circuit. Timer Data Register Consists of Timer0 HighMSB Data Register (T0HMD), Timer0 High-LSB Data Register (T0HLD), Timer0 Low-MSB Data Register (T0LMD), Timer0 Low-LSB Data Register (T0LLD), Timer1 High Data Register (T1HD), Timer1 Low Data
- 16-bit Interval Timer - 16-bit Event Counter - 16-bit Input Capture - 16-bit rectangular-wave output - 8-bit Interval Timer - 8-bit rectangular-wave output - 8-bit Interval Timer - 8-bit rectangular-wave output - Modulo-N Mode Table 13-1 Timer Operation 16bit Timer (T0) Resolution PS0 (0.25us) PS1 (0.5us) PS2 (1us) PS3 (2us) PS4 (4us) PS5 (8us) PS11 (512us) EC MAX. Count 16,384us 32,768us 65,536us 131,072us 262,144us 524,288us 33,554,432us 8bit Timer (T1) Resolution PS0 (0.25us) PS1 (0.5us) PS2 (1us) PS3 (2us) PS7 (32us) PS8 (64us) PS9 (128us) PS10 (256us) MAX. Count 64us 128us 256us 512us 8,192us 16,384us 32,768us 65,536us 8bit Timer (T2) Resolution PS5 (8us) PS6 (16us) PS7 (32us) PS8 (64us) PS9 (128us) PS10 (256us) PS11 (512us) PS12 (1024us) MAX. Count 2,048us 4,096us 8,192us 16,384us 32,768us 65,536us 131,072us 262,144us
Register (T1LD), Timer2 Data Register (T2DR). Any of the PS0 ~ PS5, PS11 and external event input EC can be selected as clock source for T0. Any of the PS0 ~ PS3, PS7 ~ PS10 can be selected as clock T1. Any of the PS5 ~ PS12 can be selected as clock source for T2. * Relevant Port Mode Register (PMR1 : 00C9h) value should be assigned for event counter.
Timer0
- Single/Modulo-N Mode - Timer Output Initial Value Setting - Timer0~Timer1 combination Logic Output - One Interrupt Generating Every 2nd Counter Overflow
Timer1
Timer2
Table 13-2 Function of Timer & Counter
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T0HMD T0LMD
T0LMD
T0LLD
T1HD
T1LD
T2DR
from EC/R14
Timer0 (16bit)
Timer1(8bit)
Timer2(8bit)
TM01
7 TO U TS TO UTB 0 T0IN IT T0O UTP BTC L T1INIT TO UT1 TO UT0
Edge Selection
from INT2/R12 (Capture Signal)
Polarity Selection
Tout Logic
T0OUT (R17)
TOUT T1OUT (REMOUT) (R16)
T2OUT (R15)
Timer 01 mode register TM01
R/W 7
R/W 6
5 -
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0 ADDRESS: 0DAH INITIAL VALUE: 00H TOUT LOGIC 00: AND of T0 OUTPUT and T1 OUTPUT 01: NAND of T0 OUTPUT and T1 OUTPUT 10: OR of T0 OUTPUT and T1 OUTPUT 11: NOR of T0 OUTPUT and T1 OUTPUT Timer1 output initial value 0: Timer1 output low 1: Timer1 output high Timer0 output initial value 0: Timer0 output low 1: Timer0 output high
TO UTS TO UTB
T0INIT T0OUTP BTCL T1INIT TO UT1 TO UT0
REMOUT Port Output Selection (TOUT Logic or TOUTB) 0: Bit(TOUTB) Output Through REMOUT 1: TOUT Logic Output Through REMOUT REMOUT Port Bit Control 0: REMOUT Output Low 1: REMOUT Output High T0OUT Polarity Selection 0: T0OUT Polarity Equal to TOUT Logic input signal 1: T0OUT Polarity Reverse to TOUT Logic input signal
Figure 13-1 Block Diagram of Timer/Counter
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IEDS[5:4]
01
INT2/R12 PIN
10 11 MSB 16 BITS LSB
IFINT2
INT2 INTERRUPT
T0HC
capture T0ST CAP0 T 0 S L [2 :0 ] E d g e D e te cto r delay 111 P S 11 PS5 PS4 PS3 PS2 PS1 PS0 110 101 100 011 010 001 000 1 0 clear
T0LC
[0D5H][0D6H]
T0IFS
EC PIN
CAP0 clear
Interrupt GEN.
IFT0
T0 COUNTER (16-bit) OUTPUT GEN.
P rescaler
Comparator
T0OUT
MUX
T0MOD T0CN
1
MUX(16-bit)
0
T0INIT
T0HMD
T0HLD
T0LMD
T0LLD
[0D3H][0D4H]
[0D5H][0D6H]
Timer 0 mode register TM0
R/W 7 C AP0
R/W 6 T0ST
R/W 5
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0 ADDRESS: 0D0H INITIAL VALUE: 00H Timer0 input clock select (fex=4Mhz) 000: PS0 250ns 001: PS1 500ns 010: PS2 1us 011: PS3 2us 100: PS4 4us 101: PS5 8us 110: PS11 512us 111: EC Timer0 Interrupt select 0: Interrupt Every Count Overflow 1: Interrupt Every 2nd Count Overflow Timer0 Single/Moudol-N select 0: Modulo-N 1: Single Mode
T0CN T0M O D T0IFS T0SL2 BTC L
T0SL1 T0SL0
Timer0 Interrupt select 0: Timer/Counter 1: Input capture (PS1:not supporting input cature) Timer0 Start/Stop control 0: Timer0 Stop 1: Tiemr0 Start after clear Timer0 Counter Continuation/Pause Control 0: Count Pause 1: Count Continuation
Figure 13-2 Block Diagram of Timer0
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T1ST
T1 COUNT REG.
T 1S L [2 :0 ] PS10 PS9 PS8 PS7 PS3 PS2 PS1 PS0
T1IFS
[0D8H] Interrupt GEN.
P rescaler
1 11 1 10 1 01 1 00 0 11 0 10 0 01 0 00
IFT1
clear
T1 COUNTER (8-bit) OUTPUT GEN.
Comparator
T1OUT
MUX
T1MOD T1CN
1
MUX(8-bit) 0
T1INIT
T1HD(8-bit) [0D7H]
T1LD(8-bit) [0D8H]
Timer 1 mode register TM1
Timer1 Start/Stop control 0: Timer1 Stop 1: Tiemr1 Start after clear
R/W 7 T1S T
R/W 6
R/W 5
R/W 4
3
R/W 2
R/W 1
R/W 0 ADDRESS: 0D1H INITIAL VALUE: 00H Timer1 input clock select (fex=4Mhz) 000: PS0 250ns 001: PS1 500ns 010: PS2 1us 011: PS3 2us 100: PS7 32us 101: PS8 64us 110: PS9 128us 111: PS10 256us
T1CN T1M O D T1IFS BTCL T1SL2
T1S L1 T1SL0
Timer1 Counter Continuation/Pause Control 0: Count Pause 1: Count Continuation
Timer1 Single/Moudol-N select 0: Modulo-N 1: Single Mode
Timer1 Interrupt select 0: Interrupt Every Count Overflow 1: Interrupt Every 2nd Count Overflow
Figure 13-3 Block Diagram of Timer1
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T2ST
T2 COUNT REG.
T 2S L [2 :0 ] PS12 PS11 PS10 PS9 PS8 PS7 PS6 PS5
[0D9H] Interrupt GEN.
P rescaler
1 11 1 10 1 01 1 00 0 11 0 10 0 01 0 00
IFT2
clear
T2 COUNTER (8-bit) OUTPUT GEN.
Comparator
T2OUT
T2DR MUX
T2CN
[0D9H]
Timer 2 mode register
7 6 5 -
R/W 4
R/W 3
R/W 2
R/W 1
R/W 0 ADDRESS: 0D2H INITIAL VALUE: 00H Timer2 input clock select (fex=4Mhz) 000: PS5 8us 001: PS6 16us 010: PS7 32us 011: PS8 64us 100: PS9 128us 101: PS10 256us 110: PS11 512us 111: PS12 1,024us
TM2
Timer2 Start/Stop control 0: Timer2 Stop 1: Tiemr2 Start after clear
-
T2ST BTC L T2SL2 T2CN
T2S L1 T2SL0
Timer2 Counter Continuation/Pause Control 0: Count Pause 1: Count Continuation
Figure 13-4 Block Diagram of Timer2
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2) Timer0, Timer1 TIMER0 and TIMER1 have an up-counter. When value of the up-counter reaches the content of Timer Data Register (TDR), the up-counter is cleared to "00h", and interrupt (IFT0, IFT1) is occured at the next clock.
T0 Data Register Value
MATCH (TDR = T0)
~~
up -
co ~~
un t ~~
T0 Value 4 3 2 1 0 0
6 5
TIME Interrupt period
Timer 0 (IFT0) Interrupt
Occur interrupt
Occur interrupt
Occur interrupt
Figure 13-5 Operation of Timer0
For Timer0, the internal clock (PS) and the external clock (EC) can be selected as counter clock. But Timer1 and Timer2 use only internal clock. As internal clock. Timer0 can be used as internal-timer which period is determined by Timer Data Register (TDR). Chosen as external clock, Timer0 executes as event-counter. The counter execution of Timer0 and Timer1 is controlled by T0CN, T0ST, CAP0, T1CN, T1ST, of Timer Mode Register TM0 and TM1. T0CN, T1CN are used to stop and start Timer0 and Timer1 without clearing the counter. T0ST, T1ST is used to clear the counter. For clearing and starting the counter, T0ST or T1ST should be temporarily set to "0" and then set to "1". T0CN, T1CN, T0ST and T1ST should be set "1", when Timer counting-up. Controlling of CAP0 enables Timer0 as input capture. By programming of CAP0 to "1", the period of signal from INT2 can be measured and then, event counter value for INT2 can be read. During counting-up, value of counter can be readTimer execution is stopped by the reset signal(RE-
SET="L")
Note: In the process of reading 16-bit Timer Data, first read the upper 8-bit data. Then read the lower 8-bit data, and read the upper 8-bit data again. If the earlier read upper 8-bit data are matched with the later read upper 8-bit data, read 16-bit data are correct. If not, caution should be taken in the selection of upper 8-bit data.
(Example) 1) Upper 8-bit Read 0A 0A 2) Lower 8-bit Read FF 01 3) Upper 8-bit Read 0B 0B ===================== 0AFF 0B01
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TDR disable enable
clear & start stop
up -c
ou n
t
~~
~ ~
TIME
Timer 0 (IFT0) Interrupt Occur interrupt T0ST Start & Stop T0ST = 0 T0CN Control count T0CN = 0 T0CN = 1 Occur interrupt
T0ST = 1
Figure 13-6 Start/Stop Operation of Timer0
T2 T3 T1 T0
INT2
Figure 13-7 Input capture operation of Timer0
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3) Single/Modulo-N Mode Timer0 (Timer1) can select initial (T0INIT, T1INIT of TM01) output level of Timer Output port. If initial level is "L", Low-Data Register value of Timer Data Register is transferred to comparator and T0OUT (T1OUT) is to be "Low", if initial level is High? High -Data Register is transferred and to be "High". Single Mode can be set by Mode Select bit (T0MOD, T1MOD) of Timer Mode Register (TM0, TM1) to "1" When used as Single Mode, Timer counts up and compares with value of Data Register. If the result is same, Time Out interrupt occurs and level of Timer Output port toggle, then counter stops as reset state. When used as Modulo-N Mode, T0MOD (T1MOD) should be set "0". Counter counts up until the value of Data Register and occurs Time-out interrupt. The level of Timer Output port toggle and repeats process of counting the value which is selected in Data Register. During Modulo-N Mode, If interrupt select bit (T0IFS, T1IFS) of Mode Register is "0", Interrupt occurs on every Time-out. If it is "1", Interrupt occurs every second timeout.
Note: Timer Output is toggled whenever time out happen
[ Single Mode ]
8bit/16bit counting
Timer Enable initial value toggle
[ Module-N Mode ]
8bit/16bit counting Timer Enable initial value toggle Timer-output toggle Int occurs (IFS=1) Each 2nd time out Int occurs (IFS=0) when Time out
Figure 13-8 Operation Diagram for Single/Modulo-N Mode
(4) Timer 2 Timer2 operates as a up-counter. The content of T2DR are compared with the contents of up-counter. If a match is found. Timer2 interrupt (IFT2) is generated and the upcounter is cleared to "00h". Therefore, Timer2 executes as a interval timer. Interrupt period is determined by the count source clock for the Timer2 and content of T2DR. When T2ST is set to "1", count value of Timer 2 is cleared and starts counting-up. For clearing and starting the Timer2. T2ST have to set to "1" after set to "0". In order to write a value directly into the T2DR, T2ST should be set to "0". Count value of Timer2 can be read at any time.
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14. INTERRUPTS
The HMS81004E/08E/16E/24E/32E interrupt circuits consist of Interrupt Mode Register (MOD), Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circuit and Master enable flag ("I" flag of PSW). 8 interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 14-1 . The HMS81004E/08E/16E/24E/32E contains 8 interrupt sources; 3 externals and 5 internals. Nested interrupt services with priority control is also possible. Software interrupt is non-maskable interrupt, the others are all maskable interrupts. - 8 interrupt source (2Ext, 3Timer, BIT, WDT and Key Scan) - 8 interrupt vector - Nested interrupt control is possible - Programmable interrupt mode (Hardware and software interrupt accept mode) - Read and write of interrupt request flag are possible. - In interrupt accept, request flag is automatically cleared.
Internal bus line I-flag is in PSW, it is cleared by "DI", set by "EI" instruction. When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by "RETI" instruction, I-flag is set to "1" by hardware.
IENL IRQL Watch Dog Timer Basic Interval Timer WDTR BITR
Interrupt Enable Register (Lower byte)
Release STOP
Priority Control
To CPU I-flag Interrupt Master Enable Flag Interrupt Vector Address Generator
IRQH Key Scan INT1 INT2 Timer 0 Timer 1 Timer 2 KSCNR INT1R INT2R T0R T1R T2R
IENH
Interrupt Enable Register (Higher byte)
Internal bus line
Figure 14-1 Block Diagram of Interrupt
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14.1 Interrupt priority and sources
Each interrupt vector is independent and has its own priority. Software interrupt (BRK) is also available. Interrupt source classification is shown in Table 14-1.
14.2 Interrupt control register
I flag of PSW is a interrupt mask enable flag. When I flag = "0", all interrupts become disable. When I flag = "1", interrupts can be selectively enabled and disabled by contents of corresponding Interrupt Enable Register. When interrupt is occured, interrupt request flag is set, and Interrupt request is detected at the edge of interrupt signal. The accepted interrupt request flag is automatically cleared during interrupt cycle process. The interrupt request flag maintains "1" until the interrupt is accepted or is cleared in program. In reset state, interrupt request flag register (IRQH, IRQL) is cleared to "0". It is possible to read the state of interrupt register and to mainpulate the contents of register and to generate interrupt. (Refer to software interrupt)
Reset/Interrupt Hardware Reset Key Scan External Interrupt1 External Interrupt2 Timer0 Timer1 Timer2 Watch Dog Timer Basic Interval Timer BRK Instruction
Symbol RESET KSCNR INT1R INT2R T0R T1R T2R WDTR BITR BRK
Priority 1 2 3 4 5 6 7 8 -
Table 14-1 Interrupt Source
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R/W
R/W
BITE -
IENL
MSB Watchdog timer
-
WDTE
ADDRESS: 0CCH INITIAL VALUE: -00- ----B LSB
Basic Interval Timer
R/W
R/W
R/W
-
R/W
T0E
R/W
T1E
R/W
T2E -
IENH
Key scan External interrupt 1 External interrupt 2
KSCNE INT1E INT2E
ADDRESS: 0CEH INITIAL VALUE: 000- 000-B LSB Timer2 Timer1 Timer0
VALUE 0: Disable 1: Enable
MSB
.
R/W
R/W
BITR -
IRQL
MSB Watchdog timer
-
WDTR
ADDRESS: 0CDH INITIAL VALUE: -00- ----B LSB
Basic Interval Timer
R/W
R/W
R/W
-
R/W
T0R
R/W
T1R
R/W
T2R -
IRQH
Key scan External interrupt 1 External interrupt 2
KSCNR INT1R INT2R
ADDRESS: 0CFH INITIAL VALUE: 000- 000-B LSB Timer2 Timer1 Timer0
MSB
Figure 14-2 Interrupt Enable & Request Flag
14.3 Interrupt accept mode
The interrupt priority order is determined by bit (IM1, IM0) of IMOD register. The condition allow for accepting interrupt is set state of the interrupt mask enable flag and the interrupt enable bit must be "1". In Reset state, these IP3 - IP0 registers become all "0".
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l
Interrupt mode register IMOD
R/W 7 R/W 6 R/W 5 IM 1 R/W 4 IM 0 R/W 3 BTCL IP 3 R/W 2 IP 2 R/W 1 IP1 R/W 0 IP0 ADDRESS: 0CAH INITIAL VALUE: --00_0000B Selection interrupt 0001: KSCNR 0010: INT1R 0011: INT2R 0101: T0R 0110: T1R 0111: T2R 1010: WDTR 1011: BITR
Priority 00: Fixed by hardware 01: Changeable by IP3~IP0 1x: Interrupt is inhibited
Figure 14-3 Interrupt Accept Mode & Selection by IP3~IP0
14.4 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an instruction. Interrupt acceptance sequence requires 8 fXIN after the completion of the current instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruction [RETI].
2. Interrupt request flag for the interrupt source accepted is cleared to "0". 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the interrupt service program is executed.
Interrupt acceptance 1. The interrupt master enable flag (I-flag) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled.
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System clock
Instruction Fetch Address Bus
PC SP SP-1 SP-2 V.L. V.H. New PC
Data Bus Internal Read Internal Write
Not used
PCH
PCL
PSW
V.L.
ADL
ADH
OP code
Interrupt Processing Step V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents.
Interrupt Service Task
Figure 14-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction registers.
External Interrupt1 Vector Table Address Entry Address
Example: Register save using push and pop instructions INTxx: PUSH PUSH PUSH A X Y ;SAVE ACC. ;SAVE X REG. ;SAVE Y REG.
0FFF8H 0FFF9H
012H 0E3H
0E312H 0E313H
0EH 2EH
interrupt processing Correspondence between vector table address for Exteranl Interrupt1 and the entry address of the interrupt service program.
POP POP POP RETI
Y X A
;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN
A interrupt request is not accepted until the I-flag is set to "1" even if a requested interrupt has higher priority than that of the current interrupt being serviced. When nested interrupt service is required, the I-flag should be set to "1" by "EI" instruction in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
General-purpose register save/restore using push and pop instructions;
main task acceptance of interrupt interrupt service task saving registers
Saving/Restoring General-purpose Register
During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. These registers are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. The following method is used to save/restore the general-purpose
restoring registers interrupt return
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14.5 BRK Interrupt
Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 14-5
Example: During Timer1 interrupt is in progress, INT1 interrupt serviced without any suspend. TIMER1: PUSH PUSH PUSH LDM LDM EI : : : : LDM LDM POP POP POP RETI A X Y IENH,#40H IENL,#00H
;Enable INT1 only ;Disable other ;Enable Interrupt
B-FLAG BRK or TCALL0 =1 BRK INTERRUPT ROUTINE RETI
=0
IENH,#0FFH ;Enable all interrupts IENL,#0FFH Y X A
TCALL0 ROUTINE Main Program service RET TIMER 1 service INT1 service
enable INT1 disable other EI
Figure 14-5 Execution of BRK/TCALL0
Occur TIMER1 interrupt
Occur INT1
14.6 Multi Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time simultaneously, an internal polling sequence determines by hardware which request is serviced. However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the Iflag is cleared to disable any further interrupt. But as user sets Iflag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress.
enable INT1 enable other
In this example, the INT1 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable "EI" in the TIMER1 routine.
Figure 14-6 Execution of Multi Interrupt
14.7 External Interrupt
The external interrupt on INT1 and INT2 pins are edge triggered depending on the edge selection register IEDS (address 0D8H) as shown in Figure14-7.
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INT1 pin
IFINT1 INT1 INTERRUPT
INT2 pin
IFINT2 INT2 INTERRUPT
2 IEDS [0CBH]
2 Edge selection Register
Ext. Int. Edge Selection reg. IEDS
7 -
6 -
W 5
W 4
W 3
W 2
1 -
0 ADDRESS: 0CBH INITIAL VALUE: 0000_0000B IED1* 01: Falling Edge Selection 10: Rising Edge Selection 11: Both Edsg Selection
IED2H IED 2L IE D1H IED1L BTCL
IED2* 01: Falling Edge Selection 10: Rising Edge Selection 11: Both Edsg Selection
Figure 14-7 External Interrupt Block Diagram
Response Time
The INT1 ~ INT2 edge are latched into IFINT1 ~ IFINT2 at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The DIV itself takes twelve cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. Figure 14-8 shows interrupt response timings.
max. 12 fXIN period
8 fXIN period
Interrupt Interrupt goes latched active
Interrupt processing
Interrupt routine
Figure 14-8 Interrupt Response Timing Diagram
14.8 Key Scan Input Processing
Key Scan Interrupt is generated by detecting low or high Input from each Input pin (R0, R1) is one of the sources which release standby (SLEEP, STOP) mode. Key Scan ports are all 16bit which are controlled by Standby Mode Release Register (SMRR0, SMRR1). Key Input is considered as Interrupt, therefore, KSCNE bit of IEHN should be set for correct interrupt executing, SLEEP mode and STOP mode, the rest of executing is the same as that of external Interrupt. Each SMRR Register bit is allowed for each port (for Bit= "0", no Key Input, for Bit= "1", Key Input available). At reset, SMRR becomes "00h". So, there is no Key Input source.
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Standby release level control register (SRLC) can select the key scan input level "L" or "H" for standby release by each bit pin (R0, R1). Standby release level control register
(SRLC) is write-only register and initialized as "00h" in reset state.
SMRR0
SRLC0
R00 R01 R 02 R 03 R 04 R 05 R 06 R 07 R10 R11 R 12 R 13 R 14 R 15 R 16 R 17
R0 PORT LOGIC
Internal Key Scan Input
R1 PORT LOGIC
SMRR1
SRLC1
W 7
W 6 KR 06
W 5 KR 05
W 4
W 3
W 2
W 1 K R01
W 0 K R00 ADDRESS: 0DCH INITIAL VALUE: 00H
SMRR0
KR 07
K R04 BTCL KR 02 KR03
KR 0* 1: Select 0: No S elect
W 7
W 6 KR 16
W 5 KR 15
W 4
W 3
W 2
W 1 K R11
W 0 K R10 ADDRESS: 0DDH INITIAL VALUE: 00H
SMRR1
KR 17
K R14 BTCL KR 12 KR13
KR 1* 1: Select 0: No S elect W 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0 ADDRESS: 0F6H INITIAL VALUE: 00H
SRLC0
KLR07 K LR06 KLR05 KLR 04 BTCL K LR02 K LR01 K LR 00 KLR03 KLR0* 1: High 0: Low W 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0
SRLC1
K LR 17 K LR 16 K LR15 KLR14 BTCL K LR 12 KLR 11 KLR10 K LR13 K LR1* 1: High 0: Low
ADDRESS: 0F7H INITIAL VALUE: 00H
Figure 14-9 Block Diagram of Key Scan Block
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15. STANDBY FUNCTION
15.1 Sleep Mode
SLEEP mode can be entered by setting the bit of SLEEP mode register (SLPM). In the mode, CPU clock stops but oscillator keeps running. B.I.T and a part of peripheral hardware execute, but prescaleris output which provide clock to peripherals can be stopped by program. (Except, PS10 can't stopped.) In SLEEP mode, more consuming power can be saved by not using other peripheral hardware except for B.I.T. By setting ENPCK (peripheral clock control bit) of CKCTLR (clock control register) to "0", peripheral hardware halted, and SLEEP mode is entered. To release SLEEP mode by BITR (basic interval timer interrupt), bit10 of prescaler should be selected as B.I.T input clock before entering SLEEP mode. "NOP" instruction should be follows setting of SLEEP mode for rising precharge time of data bus line. (ex) setting of SLEEP mode : set the bit of SLEEP ; mode register (SLPM) NOP : NOP instruction
Sleep Mode Control Register (W) SLPM -
ADDRESS : 0F0H INITIAL VALUE : -------0b 0
SLPM0 0: Sleep mode release 1: sleep mode
Clock Control Register (W) CKCTLR 7 6 5 4 3
ADDRESS : 0C7H INITIAL VALUE : --110111b 2 1 0
ENPCK
0: Stopped 1: Provided
15.2 STOP MODE
STOP mode can be entered by STOP instruction during program. In STOP mode, oscillator is stopped to make all clocks stop, which leads to less power consumption. All registers and RAM data are preserved. "NOP" instruction should be follows STOP instruction for rising precharge time of Data Bus line. (ex) STOP NOP : STOP instruction execution : NOP instruction
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OSC Circuit
Clock Pulse Generator
CPU Clock
MUX
Basic Interval Timer
Clear
Prescaler
Clear
Control Signal STOP S R Q S R Release Signal from Interrupt RESETB Q Overflow Detection
Figure 15-1 Block Diagram of Standby Circuit
15.3 STANDBY MODE RELEASE
Release of STANDBY mode is executed by RESET input and Interrupt signal. Register value is defined when Reset. When there is a release signal of STOP mode (Interrupt, RESET input), the instruction execution starts after stabilization oscillation time is set by value of BTS2 ~ BTS0 and set ENPCK to "1".
Release Signal RESETB KSCN(Key Input) INT1,INT2 B.I.T.
SLEEP O O O O
STOP O O O
Table 15-1 Release Signal of Standby Mode
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Release Factor RESETB KSCN(Key Input)
Release Method By RESETB Pin=Low level, Standby mode is releas and system is initialized Standby mode is released by low input of selected pin by key scan Input(SMRR0,SMRR1). In case of interrupt mask enable flag= "0", program executes just after standby instruction, if flag= "1" enters each interrupt service routine. When external interrupt (INT1,INT2)enable flag is "1", standby mode is released at the rising edge of each terminal. When standby mode is released at interrupt. Mask Enable flag= "0", program executes from the next instruction of standby instruction. When "1", enters each interrupt service routine. When B.I.T. is executed only by bit10 of prescaler(PS10), SLEEP mode can be released. Interrupt release SLEEP mode , when BIT interrupt enable flag is "1". When standby mode is released at interrupt. Mask enable flag= "0", program executes from the next instruction of SLEEP instruction. When "1", enters each interrupt service routine. Table 15-2
INT1,INT2
Basic Interval Timer(IFBIT)
[SLEEP MODE]
SLEEP command
Xin SLEEP mode release by interrupt RESET Longer than 2 machine cycle [STOP MODE]
Xin STOP mode release by interrupt Program setting time by CKCTLR RESET Longer than stabe OSC. Time Stable OSC.time
Figure 15-2 Block Diagram of Standby Circuit
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15.4 RELEASE OPERATION OF STANDBY MODE
After standby mode is released, the operation begins according to content of related interrupt register just before standby mode start (Figure 15-3).
STOP Command
Standby Mode
Interrupt Request GEN.
Int. enable reg. 1
0
Standby Mode Release
PSW I Flag 1
0
Interrupt Service Routine
Standby Next Command Execution
. Figure 15-3 Standby Mode Release Flow
(1) Interrupt Enable Flag(I) of PSW = "0" Release by only interrupt which interrupt enable flag = "1", and starts to execute from next to standby instruction (SLEEP or STOP). (2) Interrupt Enable Flag(I) of PSW = "1" Released by only interrupt which each interrupt enable flag = "1", and jump to the relevant interrupt service routine.
tering STOP mode, clock of bit10 (PS10) of prescaler is selected or peripheral hardware clock control bit (ENPCK) to "1", Therefore the clock necessary for stabilization oscillation time should be input into B.I.T. otherwise, standby mode is released by reset signal. In case of interrupt request flag and interrupt enable flag are both "1", standby mode is not entered.
Note: When STOP instruction is used, B.I.T should guarantee the stabilization oscillation time. Thus, just before en-
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Internal circuit Oscillator Internal CPU Register RAM I/O port Prescaler Basic Interval Timer Watch-dog Timer Timer Address Bus,Data Bus
SLEEP mode Active Stop Retained Retained Retained Active PS10 selected:Active Others: Stop Stop Stop Retained
STOP mode Stop Stop Retained Retained Retained Retained Stop Stop Stop Retained
Table 15-3 Operation State in Standby Mode
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16. RESET FUNCTION
16.1 EXTERNAL RESET
The RESET pin should be held at low for at least 2machine cycles with the power supply voltage within the operating voltage range and must be connected 0.1uF capacitor for stable system initialization. The RESET pin contains a Schmitt trigger with an internal pull-up resistor.
RESET
0.1uF capacitor GND
Figure 16-1 RESET Pin connection
16.2 POWER ON RESET
Power On Reset circuit automatically detects the rise of power voltage (the rising time should be within 50ms) the power voltage reaches a certain level, RESET terminal is maintained at "L" Level until a crystal ceramic oscillator oscillates stably. After power applies and starting of oscillation, this reset state is maintained for about oscillation cycle of 219 (about 65.5ms : at 4MHz).The execution of built-in Power On Reset circuit is as follows : (1) Latch the pulse from Power On Detection Pulse Generator circuit, and reset Prescaler, B.I.T and B.I.T Overflow detection circuit. (2) Once B.I.T Overflow detection circuit is reset. Then, Prescaler starts to count. (3) Prescaler output is inputted into B.I.T and PS10 of Prescaler output is automatically selected. If overflow of B.I.T is detected, Overflow detection circuit is set. 4) Reset circuit generates maximum period of reset pulse from Prescaler and B.I.T
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VDD
RESET
Internal Reset Power on Detect Pulse Generator GND
0.1uF GND
Clear
Clear PS10 Basic Interval Timer MSB
Clear B.I.T. Overflow Detction Circuit
OSC Circuit
Prescaler
Figure 16-2 Block Diagram of Power On Reset Circuit
Note: When Power On Reset, oscillator stabilization time doesnt include OSC. Start time.
VDD
Prescaler Count Start
OSC. Start Time
Figure 16-3 Oscillator stabiliaztion diagram
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1
2
3
4
5
6
7
~ ~
Oscillator (XIN pin) RESET
~ ~ ~ ~
ADDRESS BUS DATA BUS
?
?
?
?
FFFE FFFF Start
~~ ~~
?
?
?
?
FE
ADL
ADH
OP
Stabilization Time
ADL and ADH are start addresses of interrupt service routine as vector contents.
Figure 16-4 Timing Diagram of Reset
~ ~
RESET Process Step MAIN PROGRAM
16.3 Low Voltage Detection Mode
(1) Low voltage detection condition An on board voltage comparator checks that VDD is at the required level to ensure correct operation of the device. If VDD is below a certain level, Low voltage detector forces the device into low voltage detection mode. (2) Low Voltage Detection Mode There is no power consumption except stop current, stop mode release function is disabled. All I/O port is configured as input mode and Data memory is retained until voltage through external capacitor is worn out. In this mode, all port can be selected with Pull-up resistor by Mask option. If there is no information on the Mask option sheet ,the default pull up option (all port connect to pull-up resistor ) is selected. (3) Release of Low Voltage Detection Mode Reset signal result from new battery(normally 3V) wakes the low voltage detection mode and come into normal reset state. It depends on user whether to execute RAM clear routine or not
LVD(V) 1.85 1.80 1.75 1.70 1.65 1.60 1.55 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 Temperature (C) 40 45 50 55 60 65 70 75 80 85 90
Figure 16-5 Low Voltage vs Temperature
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(4) SRAM BACK-UP after Low Voltage Detection.
VDD
about hours depend on Vdd-GND Capacitor SRAM Data Backup 3V 2V(Min.) Low Voltage detetion point
1.7V(typ.20 C) Power on Reset (SRAM retention) 0.7V(Vret) Power on Reset (SRAM unstable)
0V
Time
User removes batteries User replaces batteries
Figure 16-6 Oscillator stabiliaztion diagram
Interrupt Stop release All I/O port Remout port OSC All I/O port pull-up on SRAM Data
disable disable input Mode Low Level STOP Mask Option retention until Vret
Table 16-1 The operation after Low Voltage detection
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(5) S/W flow chart example after Reset using SRAM Back-up
RESET
Stack Pointer initialize
Check the SRAM value (RAM Pattern, Checksum)
SRAM DATA VALID? Y
N
Use Saved SRAM value
Clear all Ram area
Main routine
Figure 16-7 S/W flow chart example after Reset using SRAM Back-up
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APPENDIX
A. MASK ORDER SHEET
MASK ORDER & VERIFICATION SHEET
HMS810
Customer should write inside thick line box. 1. Customer Information
Company Name Application Order Date Tel: Name&Signature:
YYYY MM DD
E -UE
2. Device Information
Package 24SKDIP 28SOP 28SKDIP 28PIN DIE File Name: ( .OTP) ( @27c256) 20SOP 24SOP 20PDIP
Fax:
Mask Data Check Sum
3. Inclusion of pull-up resistor in Low Volatage Detection mode
Port R00 R01 R02 R03 R04 R05 R06 R07 Y/N R10 R11 R12 R13 R14 R15 R16 R17
*1 *1 *1 *1 *2
R20 R21 R22 R23 R24
*2
*2
*2
*1 : is not avilable for 20PIN. So default option is pull-up on. *2 : is not avilable for 20PIN & 24PIN. So default option is pull-up on.
4. Marking Specification
(Please check mark into
)
04/08/16/24/32
Customer's logo
HMS810 YYWW
E -UE KOREA
Hynix ROM Code Number
HMS810 YYWW
E -UE KOREA
Customer logo is not required. If the customer logo must be used in the special mark, please submit a clean original of the logo. Customer's part number
Lot Number
5. Delivery Schedule Date Customer Sample Risk Order
YYYY YYYY MM MM DD DD
Quantity pcs pcs
Hynix Confirmation
6. ROM Code Verification
YYYY MM DD
This box is written after "6.Verification".
Approval Date:
YYYY MM DD
Verification D ate:
Please confirm our verification data.
Check Sum: Tel: Name & Signature: Fax:
I agree with your verification data and confirm you to m ake m ask set.
Tel: Name & Signature:
Fax:
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APPENDIX
B. INSTRUCTION
B.1 Terminology List
Terminology A X Y PSW #imm dp !abs [] {} { }+ .bit A.bit dp.bit M.bit rel upage n + x Accumulator X - register Y - register Program Status Word 8-bit Immediate data Direct Page Offset Address Absolute Address Indirect expression Register Indirect expression Register Indirect expression, after that, Register auto-increment Bit Position Bit Position of Accumulator Bit Position of Direct Page Memory Bit Position of Memory Data (000H~0FFFH) Relative Addressing Data U-page (0FF00H~0FFFFH) Offset Address Table CALL Number (0~15) Addition
0 Bit Position
Description
Upper Nibble Expression in Opcode
y - x / ()
1 Bit Position
Upper Nibble Expression in Opcode
Subtraction Multiplication Division Contents Expression AND OR Exclusive OR NOT Assignment / Transfer / Shift Left Shift Right Exchange Equal Not Equal
~ =
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APPENDIX
B.2 Instruction Map
LOW 00000 HIGH
00 -
00001 01 SET1 dp.bit
00010 02
00011 03
00100 04 ADC #imm SBC #imm CMP #imm OR #imm AND #imm EOR #imm LDA #imm LDM dp,#imm
00101 05 ADC dp SBC dp CMP dp OR dp AND dp EOR dp LDA dp STA dp
00110 06 ADC dp+X SBC dp+X CMP dp+X OR dp+X AND dp+X EOR dp+X LDA dp+X STA dp+X
00111 07 ADC !abs SBC !abs CMP !abs OR !abs AND !abs EOR !abs LDA !abs STA !abs
01000 08 ASL A ROL A LSR A ROR A INC A DEC A TXA
01001 09 ASL dp ROL dp LSR dp ROR dp INC dp DEC dp LDY dp STY dp
01010 0A
01011 0B
01100 0C BIT dp COM dp TST dp CMPX dp CMPY dp DBNE dp LDX dp STX dp
01101 0D POP A POP X POP Y POP PSW CBNE dp+X XMA dp+X LDX dp+Y STX dp+Y
01110 0E PUSH A PUSH X PUSH Y PUSH PSW TXSP
01111 0F BRK BRA rel PCALL Upage RET INC X DEC X DAS
000
BBS BBS A.bit,rel dp.bit,rel
TCALL SETA1 0 .bit TCALL CLRA1 2 .bit TCALL 4 TCALL 6 NOT1 M.bit OR1 OR1B
001
CLRC
010
CLRG
011
DI
100
CLRV
TCALL AND1 8 AND1B TCALL EOR1 10 EOR1B TCALL 12 TCALL 14 LDC LDCB STC M.bit
101
SETC
TSPX
110
SETG
XCN
111
EI
TAX
XAX
STOP
LOW 10000 HIGH
10 BPL rel BVC rel BCC rel BNE rel BMI rel BVS rel BCS rel BEQ rel
10001 11 CLR1
dp.bit
10010 12 BBC
A.bit,rel
10011 13 BBC
dp.bit,rel
10100 14 ADC {X} SBC {X} CMP {X} OR {X} AND {X} EOR {X} LDA {X} STA {X}
10101 15 ADC !abs+Y SBC !abs+Y CMP !abs+Y OR !abs+Y AND !abs+Y EOR !abs+Y LDA !abs+Y STA !abs+Y
10110 16 ADC [dp+X] SBC [dp+X] CMP [dp+X] OR [dp+X] AND [dp+X] EOR [dp+X] LDA [dp+X] STA [dp+X]
10111 17 ADC [dp]+Y SBC [dp]+Y CMP [dp]+Y OR [dp]+Y AND [dp]+Y EOR [dp]+Y LDA [dp]+Y STA [dp]+Y
11000 18 ASL !abs ROL !abs LSR !abs ROR !abs INC !abs DEC !abs LDY !abs STY !abs
11001 19 ASL dp+X ROL dp+X LSR dp+X ROR dp+X INC dp+X DEC dp+X LDY dp+X STY dp+X
11010 1A TCALL 1 TCALL 3 TCALL 5 TCALL 7 TCALL 9 TCALL 11 TCALL 13 TCALL 15
11011 1B JMP !abs CALL !abs MUL DBNE Y DIV XMA {X} LDA {X}+ STA {X}+
11100 1C BIT !abs TEST !abs
11101 1D ADDW dp SUBW dp
11110 1E LDX #imm LDY #imm CMPX #imm CMPY #imm INC Y DEC Y XAY
11111 1F JMP [!abs] JMP [dp] CALL [dp] RETI
000
001
010
TCLR1 CMPW !abs dp CMPX !abs CMPY !abs XMA dp LDX !abs STX !abs LDYA dp INCW dp DECW dp STYA dp CBNE dp
011
100
TAY
101
TYA
110
DAA
111
XYX
NOP
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APPENDIX
B.3 Instruction Set
Arithmetic / Logic Operation
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Mnemonic
ADC #imm ADC dp ADC dp + X ADC !abs ADC !abs + Y ADC [ dp + X ] ADC [ dp ] + Y ADC { X } AND #imm AND dp AND dp + X AND !abs AND !abs + Y AND [ dp + X ] AND [ dp ] + Y AND { X } ASL A ASL dp ASL dp + X ASL !abs CMP #imm CMP dp CMP dp + X CMP !abs CMP !abs + Y CMP [ dp + X ] CMP [ dp ] + Y CMP { X } CMPX #imm CMPX dp CMPX !abs CMPY #imm CMPY dp CMPY !abs COM dp DAA DAS DEC A DEC dp DEC dp + X DEC !abs DEC X DEC Y
Op Code
04 05 06 07 15 16 17 14 84 85 86 87 95 96 97 94 08 09 19 18 44 45 46 47 55 56 57 54 5E 6C 7C 7E 8C 9C 2C DF CF A8 A9 B9 B8 AF BE
Byte No
2 2 2 3 3 2 2 1 2 2 2 3 3 2 2 1 1 2 2 3 2 2 2 3 3 2 2 1 2 2 3 2 2 3 2 1 1 1 2 2 3 1 1
Cycle No
2 3 4 4 5 6 6 3 2 3 4 4 5 6 6 3 2 4 5 5 2 3 4 4 5 6 6 3 2 3 4 2 3 4 4 3 3 2 4 5 5 2 2 Arithmetic shift left
C
Operation
Add with carry. A(A)+(M)+C
Flag
NVGBHIZC
NV--H-ZC
Logical AND A (A)(M) N-----Z-
76543210
N-----ZC
"0"
Compare accumulator contents with memory contents (A) -(M)
N-----ZC
Compare X contents with memory contents (X)-(M) Compare Y contents with memory contents (Y)-(M) 1'S Complement : ( dp ) ~( dp ) Decimal adjust for addition Decimal adjust for subtraction Decrement M (M)-1 N-----ZC N-----ZC
N-----ZN-----ZC N-----ZC N-----ZN-----ZN-----ZN-----ZN-----ZN-----Z-
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APPENDIX
No.
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 DIV
Mnemonic
Op Code
9B A4 A5 A6 A7 B5 B6 B7 B4 88 89 99 98 8F 9E 48 49 59 58 5B 64 65 66 67 75 76 77 74 28 29 39 38 68 69 79 78 24 25 26 27 35 36 37 34 4C CE
Byte No
1 2 2 2 3 3 2 2 1 1 2 2 3 1 1 1 2 2 3 1 2 2 2 3 3 2 2 1 1 2 2 3 1 2 2 3 2 2 2 3 3 2 2 1 2 1
Cycle No
12 2 3 4 4 5 6 6 3 2 4 5 5 2 2 2 4 5 5 9 2 3 4 4 5 6 6 3 2 4 5 5 2 4 5 5 2 3 4 4 5 6 6 3 3 5 Subtract with Carry Logical shift right Increment M (M)+1 Exclusive OR A (A)(M)
Operation
Divide : YA / X Q: A, R: Y
Flag
NVGBHIZC NV--H-Z-
EOR #imm EOR dp EOR dp + X EOR !abs EOR !abs + Y EOR [ dp + X ] EOR [ dp ] + Y EOR { X } INC A INC dp INC dp + X INC !abs INC X INC Y LSR A LSR dp LSR dp + X LSR !abs MUL OR #imm OR dp OR dp + X OR !abs OR !abs + Y OR [ dp + X ] OR [ dp ] + Y OR { X } ROL A ROL dp ROL dp + X ROL !abs ROR A ROR dp ROR dp + X ROR !abs SBC #imm SBC dp SBC dp + X SBC !abs SBC !abs + Y SBC [ dp + X ] SBC [ dp ] + Y SBC { X } TST dp XCN
N-----Z-
N-----ZC N-----ZN-----ZN-----ZN-----ZN-----Z-
76543210 C "0"
N-----ZC
Multiply : YA Y x A Logical OR A (A)(M)
N-----Z-
N-----Z-
Rotate left through Carry
C 76543210
N-----ZC
Rotate right through Carry
76543210 C
N-----ZC
A ( A ) - ( M ) - ~( C ) NV--HZC
Test memory contents for negative or zero, ( dp ) - 00H Exchange nibbles within the accumulator A7~A4 A3~A0
N-----ZN-----Z-
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APPENDIX
Register / Memory Operation
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Mnemonic
LDA #imm LDA dp LDA dp + X LDA !abs LDA !abs + Y LDA [ dp + X ] LDA [ dp ] + Y LDA { X } LDA { X }+ LDM dp,#imm LDX #imm LDX dp LDX dp + Y LDX !abs LDY #imm LDY dp LDY dp + X LDY !abs STA dp STA dp + X STA !abs STA !abs + Y STA [ dp + X ] STA [ dp ] + Y STA { X } STA { X }+ STX dp STX dp + Y STX !abs STY dp STY dp + X STY !abs TAX TAY TSPX TXA TXSP TYA XAX XAY XMA dp XMA dp+X XMA {X} XYX
Op Code
C4 C5 C6 C7 D5 D6 D7 D4 DB E4 1E CC CD DC 3E C9 D9 D8 E5 E6 E7 F5 F6 F7 F4 FB EC ED FC E9 F9 F8 E8 9F AE C8 8E BF EE DE BC AD BB FE
Byte No
2 2 2 3 3 2 2 1 1 3 2 2 2 3 2 2 2 3 2 2 3 3 2 2 1 1 2 2 3 2 2 3 1 1 1 1 1 1 1 1 2 2 1 1
Cycle No
2 3 4 4 5 6 6 3 4 5 2 3 4 4 2 3 4 4 4 5 5 6 7 7 4 4 4 5 5 4 5 5 2 2 2 2 2 2 4 4 5 6 5 4 Load Y-register Y(M) Load accumulator A(M)
Operation
Flag
NVGBHIZC
N-----Z-
X- register auto-increment : A ( M ) , X X + 1 Load memory with immediate data : ( M ) imm Load X-register X (M) N-----Z--------
N-----Z-
Store accumulator contents in memory (M)A --------
X- register auto-increment : ( M ) A, X X + 1 Store X-register contents in memory (M) X Store Y-register contents in memory (M) Y Transfer accumulator contents to X-register : X A Transfer accumulator contents to Y-register : Y A Transfer stack-pointer contents to X-register : X sp Transfer X-register contents to accumulator: A X Transfer X-register contents to stack-pointer: sp X Transfer Y-register contents to accumulator: A Y Exchange X-register contents with accumulator :X A Exchange Y-register contents with accumulator :Y A Exchange memory contents with accumulator (M)A Exchange X-register contents with Y-register : X Y N-----Z----------------------
N-----ZN-----ZN-----ZN-----ZN-----ZN-----Z---------------
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APPENDIX
16-BIT operation
No.
1 2 3 4 5 6 7
Mnemonic
ADDW dp CMPW dp DECW dp INCW dp LDYA dp STYA dp SUBW dp
Op Code
1D 5D BD 9D 7D DD 3D
Byte No
2 2 2 2 2 2 2
Cycle No
5 4 6 6 5 5 5
Operation
16-Bits add without Carry YA ( YA ) ( dp +1 ) ( dp ) Compare YA contents with memory pair contents : (YA) - (dp+1)(dp) Decrement memory pair ( dp+1)( dp) ( dp+1) ( dp) - 1 Increment memory pair ( dp+1) ( dp) ( dp+1) ( dp ) + 1 Load YA YA ( dp +1 ) ( dp ) Store YA ( dp +1 ) ( dp ) YA 16-Bits subtract without carry YA ( YA ) - ( dp +1) ( dp)
Flag
NVGBHIZC NV--H-ZC N-----ZC N-----ZN-----ZN-----Z-------NV--H-ZC
Bit Manipulation
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mnemonic
AND1 M.bit AND1B M.bit BIT dp BIT !abs CLR1 dp.bit CLRA1 A.bit CLRC CLRG CLRV EOR1 M.bit EOR1B M.bit LDC M.bit LDCB M.bit NOT1 M.bit OR1 M.bit OR1B M.bit SET1 dp.bit SETA1 A.bit SETC SETG STC M.bit TCLR1 !abs TSET1 !abs
Op Code
8B 8B 0C 1C y1 2B 20 40 80 AB AB CB CB 4B 6B 6B x1 0B A0 C0 EB 5C 3C
Byte No
3 3 2 3 2 2 1 1 1 3 3 3 3 3 3 3 2 2 1 1 3 3 3
Cycle No
4 4 4 5 4 2 2 2 2 5 5 4 4 5 5 5 4 2 2 2 6 6 6
Operation
Bit AND C-flag : C ( C ) ( M .bit ) Bit AND C-flag and NOT : C ( C ) ~( M .bit ) Bit test A with memory : Z ( A ) ( M ) , N ( M 7 ) , V ( M6 ) Clear bit : ( M.bit ) "0" Clear A bit : ( A.bit ) "0" Clear C-flag : C "0" Clear G-flag : G "0" Clear V-flag : V "0" Bit exclusive-OR C-flag : C ( C ) ( M .bit ) Bit exclusive-OR C-flag and NOT : C ( C ) ~(M .bit) Load C-flag : C ( M .bit ) Load C-flag with NOT : C ~( M .bit ) Bit complement : ( M .bit ) ~( M .bit ) Bit OR C-flag : C ( C ) ( M .bit ) Bit OR C-flag and NOT : C ( C ) ~( M .bit ) Set bit : ( M.bit ) "1" Set A bit : ( A.bit ) "1" Set C-flag : C "1" Set G-flag : G "1" Store C-flag : ( M .bit ) C Test and clear bits with A : A - ( M ) , ( M ) ( M ) ~( A ) Test and set bits with A : A-(M), (M) (M)(A)
Flag
NVGBHIZC -------C -------C MM----Z-
---------------------0 --0-----0--0---------C -------C -------C -------C --------------C -------C ---------------------1 --1-----------N-----ZN-----Z-
lxxvi
JUNE 2001 Ver 1.00
APPENDIX
Branch / Jump Operation
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mnemonic
BBC A.bit,rel BBC dp.bit,rel BBS A.bit,rel BBS dp.bit,rel BCC rel BCS rel BEQ rel BMI rel BNE rel BPL rel BRA rel BVC rel BVS rel CALL !abs CALL [dp] CBNE dp,rel CBNE dp+X,rel DBNE dp,rel DBNE Y,rel JMP !abs JMP [!abs] JMP [dp] PCALL upage
Op Code
y2 y3 x2 x3 50 D0 F0 90 70 10 2F 30 B0 3B 5F FD 8D AC 7B 1B 1F 3F 4F
Byte No
2 3 2 3 2 2 2 2 2 2 2 2 2 3 2 3 3 3 2 3 3 2 2
Cycle No
4/6 5/7 4/6 5/7 2/4 2/4 2/4 2/4 2/4 2/4 4 2/4 2/4 8 8 5/7 6/8 5/7 4/6 3 5 4 6 Branch if bit clear :
Operation
if ( bit ) = 0 , then pc ( pc ) + rel Branch if bit set : if ( bit ) = 1 , then pc ( pc ) + rel Branch if carry bit clear if ( C ) = 0 , then pc ( pc ) + rel Branch if carry bit set if ( C ) = 1 , then pc ( pc ) + rel Branch if equal if ( Z ) = 1 , then pc ( pc ) + rel Branch if minus if ( N ) = 1 , then pc ( pc ) + rel Branch if not equal if ( Z ) = 0 , then pc ( pc ) + rel Branch if plus if ( N ) = 0 , then pc ( pc ) + rel Branch always pc ( pc ) + rel Branch if overflow bit clear if (V) = 0 , then pc ( pc) + rel Branch if overflow bit set if (V) = 1 , then pc ( pc ) + rel Subroutine call M( sp)( pcH ), spsp - 1, M(sp) (pcL), sp sp - 1, if !abs, pc abs ; if [dp], pcL ( dp ), pcH ( dp+1 ) . Compare and branch if not equal : if ( A ) ( M ) , then pc ( pc ) + rel. Decrement and branch if not equal : if ( M ) 0 , then pc ( pc ) + rel. Unconditional jump pc jump address U-page call M(sp) ( pcH ), sp sp - 1, M(sp) ( pcL ), sp sp - 1, pcL ( upage ), pcH "0FFH" . Table call : (sp) ( pcH ), sp sp - 1, M(sp) ( pcL ),sp sp - 1, pcL (Table vector L), pcH (Table vector H)
Flag
NVGBHIZC ---------------
----------------------------------------------------------------
---------------
--------
--------
--------
24
TCALL n
nA
1
8
--------
JUNE 2001 Ver 1.00
lxxvii
APPENDIX
Control Operation & Etc.
No.
1 2 3 4 5 6 7 8 9 10 11 12 13
Mnemonic
BRK DI EI NOP POP A POP X POP Y POP PSW PUSH A PUSH X PUSH Y PUSH PSW RET
Op Code
0F 60 E0 FF 0D 2D 4D 6D 0E 2E 4E 6E 6F
Byte No
1 1 1 1 1 1 1 1 1 1 1 1 1
Cycle No
8 3 3 2 4 4 4 4 4 4 4 4 5
Operation
Software interrupt : B "1", M(sp) (pcH), sp sp-1, M(s) (pcL), sp sp - 1, M(sp) (PSW), sp sp -1, pcL ( 0FFDE H ) , pcH ( 0FFDFH) . Disable all interrupts : I "0" Enable all interrupt : I "1" No operation sp sp + 1, A M( sp ) sp sp + 1, X M( sp ) sp sp + 1, Y M( sp ) sp sp + 1, PSW M( sp ) M( sp ) A , sp sp - 1 M( sp ) X , sp sp - 1 M( sp ) Y , sp sp - 1 M( sp ) PSW , sp sp - 1 Return from subroutine sp sp +1, pcL M( sp ), sp sp +1, pcH M( sp ) Return from interrupt sp sp +1, PSW M( sp ), sp sp + 1, pcL M( sp ), sp sp + 1, pcH M( sp ) Stop mode ( halt CPU, stop oscillator )
Flag
NVGBHIZC ---1-0------0------1---------
-------restored
--------
--------
14 15
RETI STOP
7F EF
1 1
6 3
restored --------
lxxviii
JUNE 2001 Ver 1.00

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